A Block-Floating-Point Processor for Rapid Application Development
Hiroaki Tanaka, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai, Shiro Kobayashi · 2007
This paper proposes an instruction set processor which uses hierarchical block-floating-point (H-BFP) arithmetic. H-BFP has been developed to provide efficient development approach for digital signal processing system. H-BFP offers highly abstracted computation model, and leads to cost-effective implementation. However, application development based on H-BFP is still time consuming task because of lacking high level programming language. In this paper, a processor architecture together with a set of instructions to support H-BFP are proposed. We also propose a related software development environment for efficient algorithm translation which generate high performance codes without any time consuming task. Experimental results show proposed environment achieves high performance signal processing systems with H-BFP processors.