Automatic Generation of Instructions to Robustly Test Delay Defects in Processors
Sankar Gurumurthy, Ramtilak Vemu, Jacob A. Abraham, Daniel G. Saab · Proceedings/Proceedings - European Test Workshop · 2007
We present a technique for generating instruction sequences to test a processor functionally. We target delay defects with this technique using an ATPG engine to generate delay tests locally, a verification engine to map the tests globally, and a feedback mechanism that makes the entire procedure faster. We demonstrate nearly 96% coverage of delay faults with the instruction sequences generated. These instruction sequences can be loaded into the cache to test the processor functionally.