A Low Energy Network-on-Chip Fabric for 3-D Multi-Core Architectures
Vivek S. Nandakumar, Malgorzata Marek-Sadowska · IEEE Journal on Emerging and Selected Topics in Circuits and Systems · 2012
In this paper, we study the network-on-chip (NoC) implemented with new vertical slit field effect transistors (VeSFETs). The unique properties of VeSFET circuits allow for very efficient power saving techniques that are not possible in complementary metal-oxide-semiconductor-based homogeneous 3-D NoCs. We demonstrate that the proposed 3-D hybrid architecture shows significant improvements in all network parameters including latency, power, and energy consumption compared to other practical 3-D NoCs.