A 32-bit NMOS microprocessor with a large register file
Robert W. Sherburne, Manolis G. H. Katevenis, David A. Patterson, Carlo H. Séquin · IEEE Journal of Solid-State Circuits · 1984
Two scaled versions of a 32-bit NMOS reduced-instruction-set computer CPU, called RISC II, have been implemented on two different processing lines using the simple layout rules of C.A. Mead and L.A. Conway (1980). The lambda values are 2 and 1.5 /spl mu/m, corresponding to drawn gate lengths of 4 and 3 /spl mu/m, respectively. The design utilizes a small set of simple instructions in conjunction with a large register file in order to provide high performance. This approach has resulted in two surprisingly powerful single-chip processors.