Hardware/software co-simulation in a VHDL-based test bench approach
Matthias Bauer, Wolfgang Ecker · 1997
Novel test bench techniques are required to cope with afunctional test complexity which is predicted to grow muchmore strongly than design complexity. Our test benchapproach attacks this complexity by using a stronghierarchical architecture, application domain-independentsynchronization, reusable modules, and easy incrementalextendability based on table-driven techniques. In addition,the integration of VHDL/C co-simulation under the controlof the test bench makes it possible to use the hardware modelfor software testing and vice versa and thus enables extremereductions in test bench coding. The efficiency of our testbench has already been demonstrated in several industrialprojects, among them a four-ASIC ATM board with oneembedded core and one external micro controller.