An evolutionary 3D over-the-cell router
B.M. Goni, Tughrul Arslan · 2003
This paper reports on a new algorithm which carries out combined 3D (4-layer) and over-the-cell (OTC) routing in order to reduce chip area in 3D VLSI technology. In order to cope with the complexity of the search space, the algorithm is tailored around a class of heuristic techniques called genetic algorithms. Our results indicate up to 62% savings in chip area when compared to conventional multilayer channel routers, using several internationally well known benchmarks.