A unified approach for the synthesis of self-testable finite state machines
Bernhard Eschermann, Hans-Joachim Wunderlich · 1991
Conventionallyself-test hardware is added after synthesis is completed.For highly sequential circuits like controllers this design method either leads to high hardware overheads or compromises fault coverage.In this paper we outline a unified approach for considering self-test hardware like pattern generators and signature registers during synthesis.Three novel target structures are present@ and a method for designing parallel self-testable circuits is discussed in more detail.For a collection of benchmark circuits we show that hardware overheads for self-testable circuits can be significantly reduced this way without sacriilcing testability.