Algorithm level recomputing using allocation diversity: a register transfer level approach to time redundancy-based concurrent error detection
Kaijie Wu, Ramesh Karri · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2002
In this paper, the authors propose an algorithm-level time redundancy-based concurrent error detection (CED) scheme against permanent and transient faults by exploiting the hardware allocation diversity at the register transfer level. Although the normal computation and the recomputation are carried out on the same data path, the operation-to-operator allocation for the normal computation is different from the operation-to-operator allocation for the recomputation. The authors show that the proposed scheme provides very good CED capability with very low area overhead.