AS/400 TM 64-bit PowerPC TM -Compatible Processor Implementaiton.
John M. Borkenhagen, Glen H. Handlogten, John D. Irish, Sheldon B. Levenstein · 1994
implementation of the 64-bit PowerPC Architecturen' optimized for the IBM AS,,400 Commercial environment is described in this paper. This 64-bit BiCMOS semicustom implementation runs al a clock rate of 170 MHz. The processor features a 4-way superscalar pipelined fixed point unit which can dispatch and execute up to 4 instructions each cycle, a floating point unit with a peak rate of 500 MFLOPs, 8-Kbyte LO instnution cache, 256-Kbyre LI cache, and support for 64-Gbyte of main storage. A 4-way tightly-coupled symmetric multi-processor system is one of several configurations supported by this implementation.