Fpga interconnect delay fault testing
E. Chmelaf · 2004
Interconnection networks consume the majority of the die area in an FPGA. Presented is a scalable manufacturing test method for all SRAM-based FPGAs, able to detect multiple delay and/or bridging interconnection faults. This method achieves an adjustable, maximum sensitivity to resistive open defects of several kilo-ohms. Bridging faults modeled as either wired-AND or wired-OR are detectable. Finally, fast and simple fault localization is presented.