Experiences with Soft-Core Processor Design
Franjo Plavec, Blair Fort, Zvonko G. Vranesic, Stephen Dean Brown · 2005
Soft-core processors exploit the flexibility of field programmable gate arrays (FPGAs) to allow a system designer to customize the processor to the needs of a target application. This paper describes the UT Nios implementation of Altera's Nios architecture. A benchmark set appropriate for soft-core processors is defined. Using the benchmark set, the performance of UT Nios is explored and compared with the commercial implementation.