An 8*8 discrete cosine transform chip with pixel rate clocks
L.J. D'Luna, William A. Cook, R. Michael Guidash, G.W. Brown, Timothy J. Tredwell, J. Fischer, T. Tarn · Third Annual IEEE Proceedings on ASIC Seminar and Exhibit · 2002
Image compression is an established means of meeting storage and transmission requirements for image data. One method is transform domain compression using the two-dimensional discrete cosine transform (DCT) on 8*8 image blocks. A 2- mu m CMOS chip that computes this transform in real-time using clocks that are no faster than the pixel rate is described. The architecture uses a distributed arithmetic processing scheme to compute two one-dimensional transforms interposed with an unconventional matrix transpose RAM. The design methodology that includes layout, simulation, verification and test, using a silicon compiler tool-set, is described.>