Performance of multiple links over single link in STC104 networks
Hyo Jong Lee, Byeong Yeol Song · 2002
There is a great demand for an efficient and reliable router in high performance parallel processing systems or data management networks. The fast routing chip, Inmos STC104 has been designed and now available in the market. The performance and characteristics of each different network topology, multistage networks, meshes, tori, and N-cubes are vital information to make decision on an appropriate network. This paper reviews the technology utilized in a fast packet switch STC104 and studies reliable routing algorithms for various network configurations. The performances of several configurations under a single link and multiple links environment are also simulated and compared.