Efficient pipelined tunable heterodyne notch filter implementation in FPGAs
Akbar Azam, Dhinesh Sasidaran, Karl E. Nelson, Gary E. Ford, Louis G. Johnson, Michael A. Soderstrand · 2002
Through a combination of multiplexing and pipelining it is possible to implement in FPGAs a high-order tunable IIR notch filter using a new digital heterodyne technique. The notch center frequency can be tuned from DC to the Nyquist frequency and the characteristics of the IIR generated notch filter can be reprogrammed for specific applications. A specific implementation of a notch filter suitable for processing digital audio has a sampling frequency of 48 kHz and a maximum clock frequency of 192 kHz, well within the operating range of modern FPGA's. The whole system can be easily retargeted for an ASIC process such as that available through MOSIS.