Multidimensional Test Escape Rate Modeling
Kenneth M. Butler, John M. Carulli, J. Saxena, Amit Nahar, W.R. Daasch · IEEE Design & Test of Computers · 2009
Today's SoC designs contain many types of circuitry, each with various test types. This article revisits the classic test escape models and highlights their limitations in a test environment with different types of circuits and different test types with overlapping coverage. A new methodology for test escape rate prediction is presented.