A single chip multimedia video processor
K. Balmer, N.K. Ing-Simmons, P. Moyse, I. Robertson, J.D. Keay, M. Hammes, E. Oakland, Richard P. Simpson, Giles Barr, Derek Roskell · 2002
This paper describes the architecture of a "state of the art" scalable DSP processing system on a single chip. The chip is called the Multimedia Video Processor (MVP) and is the performance flagship of the Texas Instruments TMS320 DSP processor family. This chip utilizes an enhanced 0.5 /spl mu/m triple-level metal 16M DRAM CMOS process. This highly programmable chip, which can sustain over two billion RISC-like operations per second will be used in systems requiring combinations of graphics acceleration, image processing, encoding/decoding compression processing, for example JPEG, MPEG (audio and video), P/spl times/64 standards as well as proprietary compression algorithms. The MVP creates a new frontier of applications for DSP processing.>