Low Complexity Digit-Serial Multiplier over GF(2^m) Using Karatsuba Technology
Trong‐Yen Lee, Min-Jea Liu, Chia-Chen Fan, Chia‐Chun Tsai, Haixia Wu · 2013
This paper presents a low complexity digit-serial GF(2m) multiplier. The proposed architecture use digit-serial combination Karatsuba multiplier to reduce area complexity of the circuit. This circuit is suitable for elliptic curve cryptography (ECC) technology. We know that the password system operation core is a multiplier. However that password system multiplier is very big, so it is necessary to reduce the area and time complexity. Therefore, this paper design and implement three smaller multipliers and digit-serial in FPGA to reduce time and area complexity. This method uses 3dm/2 ANDs, (6m+n+3dm/2+m/2+d-7) XORs and (3m-3) registers. Take GF(2340) example, the proposed method compares with related works [12] and [14] which can reduce 70.7% and 50.79% on area, respectively and reduce 50.9% and 73.5% on time, respectively.