A chip set architecture for programmable real-time MPEG2 video encoder
Takeshi Matsumura, Hiroshi Segawa, Shiro Matsuura, A. Hanami, H. Yamaoka, R. Streitenberger, S. Nakagawa, K. Ishihara, Tadashi Kasezawa, Yoshiaki Ajioka, Atsushi Maeda, Masahiko Yoshimoto · 2002
This paper describes a chip set architecture for a programmable video encoder based on the MPEG2 main profile at main level (MP@ML). The chip set consists of a Controller-LSI (C-LSI), a macroblock level Pixel Processor-LSI (P-LSI) and a Motion Estimation-LSI (ME-LSI). The chip set combined with synchronous DRAMs (SDRAM) supports the whole layer processing including rate-control and realizes the real-time encoding for ITU-R-601 resolution video (720/spl times/480 pixels at 30 frame/s) with glueless logic. The exhaustive motion estimation capability is scalable up to +-63.5/+-15.5 in the horizontal/vertical directions. This chip set solution can realize a low cost MPEG2 video encoder system with excellent video quality on a small PC card.