Test generation for presettable synchronous sequential circuits
Jhing-Fa Wang, Tah-Yuan Kuo, Pao-Chuan Chen, Jau‐Yien Lee · International Symposium on VLSI Technology, Systems, and Applications · 2003
A test generation system for presettable synchronous sequential circuits is presented. The main goals is to obtain a test sequence as short as possible for a given circuit. To do this, the authors introduce a measure called minimum output distance (MOD), which can help select the target faults to test so that the expected test length and computing time can be reduced. Experimental results for several circuits are given, showing that the system can achieve very high fault coverage within a reasonable time.>