Error correction for combinational logic circuits
G Geeke Bruin-Muurling, Richard P. Kleihorst, NF Benschop, RJ van der Vleuten, Juriaan Simonis · TU/e Research Portal · 2000
In this paper we propose a method for error-correction in IC implementations of Boolean functions. The method corrects both manufacturing "hard" errors and temporary "soft" errors during curcuit operation. The errors in the logic are detected and corrected by additional logic implemented on each IC. The method proposed can correct output errors. Experimental results prove the feasibility of our method. we have a theoretical upperbound of a factor of 2n+1 in complexity increase of the total circuit, for this method for correction of n errors.