Low-cost variable-length FFT processor for DVB-T/H applications
Kisun Jung, Hanho Lee · 2010
This paper presents a low-cost variable-length FFT processor for digital video broadcasting - terrestrial / handheld (DVB-T/H) systems employing pipelined shared-memory architecture, in which a radix-2/23/24FFT algorithm, multi-path delay commutator (MDC), a novel data scaling approach are exploited. Based on this architecture, novel low cost index block scaling approach was proposed to increase area efficiency. Also, an elaborate memory configuration scheme applied to make single-port SRAM without degrading throughput rate. The SQNR performance of this FFT processor has signal-to-quantization noise ratio (SQNR) of 8K-point FFT is about 46.8 dB at 11bit internal word length for QPSK/16QAM modulation. The maximum clock frequency of proposed design is 110 MHz.