A neural algorithm for reconstructing mesh-connected processor arrays using single-track switches
Itsuo Takanami, K. Kurata, Takahiro Watanabe · 2002
To overcome faults in mesh-connected processor arrays, a number of reconfiguration schemes have been studied in the literature. One of them, the mesh-connected processor arrays model based on single-track switches, has been proposed in. The model has the advantage of its inherent simplicity of the routing hardware. So far, some algorithms have been proposed to solve the problem of reconfiguration for this model. For example, a polynomial time algorithm has been presented. However, it needs global information on fault distribution and it seems to be a troublesome job to implement the algorithm even by software while it may be impossible to implement it by hardware. In this paper, using a Hopfield-type neural network model, we present an algorithm for reconstructing the mesh-connected processor arrays using single-track switches and show its effectiveness by computer simulation. Furthermore, we present a hardware implementation of the neural algorithm by which a self-repair system can be realized.