Speech synthesis software for a 32-bit microprocessor
Y. Ishikawa, Y. Kisuki, Tadashi Sakamoto, Tomohiro Hase · IEEE Transactions on Consumer Electronics · 1998
The achievements in developing a new speech synthesis algorithm with reduced computation and memory consumption as well as the implementation technology centered on the specialized embedded MCU architecture are described in this paper. To cope with these challenges, a method using 1-pitch waveforms with a common phase is proposed. In addition, data relocation in the memory was used to improve the cache hit rate. The floating-point computation was altered to a 16-bit fixed-point computation to reduce the load on a CPU not equipped with an FPU. The performance of the speech synthesis software was verified and evaluated by making a model system incorporating all the aforementioned features. The necessary memory size proven by the evaluation test was 420 kbytes. The data processing time was also reduced by 25% by relocating the codes and data in the memory. The use of fixed-point computation produced a processing speed forty times as high as the floating-point computation. As a result, the total computation amount of this speech synthesis software was proven to be 1 to 1.5 MIPS.