Design and Standardization of Low-Density Parity-Check Codes for Space Applications
Kenneth S. Andrews, D. Divsalar, Sam Dolinar, Jon Hamkins, Fabrizio Pollara · SpaceOps 2008 Conference · 2008
In the last decade, a family of 16 low-rate turbo codes were designed and standardized, and decoders were built for each of the three ground complexes of the Deep Space Network (DSN). These codes are now flying on several missions, including MRO, MESSENGER, and STEREO. A brief summary of the turbo code family is presented, along with a performance and complexity comparison to NASA’s legacy codes. In the last few years, exciting research developments have produced ten higher rate low-density parity-check (LDPC) codes for the high-data-rate missions anticipated in the coming decades. Originally invented by R. Gallager in his PhD thesis in 1960, this coding technique was largely forgotten for more than 30 years. The primary advance in LDPC codes is the discovery of an iterative decoding algorithm, now called Belief Propagation (BP) decoding, which offers near-optimum performance for large linear LDPC codes at a manageable complexity. The performance gains of LDPC codes were difficult to realize technologically in the early 1960s. Several decades of VLSI development have finally made the implementation of these codes practical. The renaissance of LDPC codes did not mark the end of turbo codes, however. LDPC codes have performance and complexity advantages over turbo codes at high code rates, but turbo codes are currently still the best solution for the lower code rates. This natural partition means that the standard family of turbo codes at rates 1/6, 1/4, 1/3, and 1/2 can live in harmony with a proposed standard of LDPC codes at rates 1/2, 2/3, 4/5, and 7/8. LDPC codes hold the promise of significantly lower decoding complexity and error-floors than turbo codes, while still achieving near-capacity performance. A summary is presented of the performance and complexity of the LDPC code family and related codes developed by NASA, along with a description of recent FPGA implementations at speeds in excess of 100 Msps. Synchronization aspects at low SNR are also discussed, and the status of infusion of this new technology in NASA missions is addressed. Standardization of LDPC codes by the CCSDS has proven challenging. In part, this is because the class of LDPC codes is very large, and their differences can be small. There is also a long list of desirable attributes, and no code is superior in all categories. The status of the standardization process is described, including a discussion of the advantages and disadvantages of the proposed candidates.