The matrix transform chip
S. Koteswara Rao · 2003
The matrix transform chip (MTC) is designed to perform matrix computations of the form Y=UDV where D is the input data matrix of 16-bit twos complement fixed-point numbers and U, V, are arbitrary coefficient matrices of the same precision. The data matrix D is input to the chip in raster scanned order at a maximum sample rate of 40 MHz, and the output matrix is provided in the same order. On a single chip, the maximum dimension of all matrices must be less than eight, but multiple chips can be cascaded to obtain arbitrary dimensions. The MTC consists of 16 16-bit parallel multipliers/40-bit accumulators, a kilobyte of dual-ported transposition static RAM, and a kilobyte of coefficient static RAM, arranged to interact in a regular iterative architecture. At peak operation, the MTC is capable of performing 0.64 billion fixed-point multiples, 0.64 billion 40-bit accumulates, along with 1.92 billion pseudorandom memory-access operations per second.>