Parallel Circuit Simulation via Binary Link Formulations (PvB)
Douglas Paul, Michel S. Nakhla, Ramachandra Achar, Natalie M. Nakhla · IEEE Transactions on Components Packaging and Manufacturing Technology · 2013
As circuit sizes increase, a means to improve the performance of simulations without sacrificing the accuracy of the results becomes increasingly essential. To achieve this goal, a new parallel algorithm is presented that allows modern multicore processors to be exploited to realize this performance improvement. These improvements are obtained without sacrificing accuracy or resorting to iterative techniques. The computational complexity of the new algorithm is compared with the previously published algorithms based on the domain decomposition (DD) technique. A mathematical proof is presented showing that in the case of the DD algorithm, the CPU cost per iteration as a function of the number of linksLbetween partitions is in the order ofO(L2), leading to poor scalability as the number of partitions increases. On the other hand, the proposed algorithm exhibits superior scalability as its complexity increases only in the order ofO(L). This result has been verified numerically and the scalability of the proposed algorithm is demonstrated with several industrial examples.