4GHz+ low-latency fixed-point and binary floating-point execution units for the POWER6 processor
Brian Curran, Bradley D. McCredie, Leon Sigal, Eric M. Schwarz, Bruce Fleischer, Yiu-Hing Chan, Daniel Webber, M. T. Vaden, Aakashdeep Goyal · 2006
A 1-pipe stage, low-latency, 13 FO4, 64b fixed-point execution unit, implemented in a 65nm SOI CMOS process, allows back-to-back execution of data dependent adds, subtracts, compares, shifts, rotates, and logical operations. A 7-pipe stage, 91 FO4, double-precision floating-point unit allows forwarding of dependent results after 6 cycles in most cases