A method for detecting interconnect DSM defects in systems on chip
Shih-Yu Yang, C. Papachristou · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2005
This paper presents a built-in test method targeting interconnect defects using I/sub DDT/ testing, delay testing, and boundary scan. It was learned that I/sub DDT/ testing is an effective way to detect open and short defects. Boundary scan can provide accessibility to internal buses inside a chip. A statistical analysis method eases the uncertain factors due to process variations and power fluctuation. This paper also includes the experimental data using the proposed techniques to detect shorts, opens, or the other non-stuck-at fault type defects.