Generation of software tools from processor descriptions for hardware/software codesign
M. R. Hartoog, James A. Rowson, P Dileep Kumar Reddy, Soumya Desai, Douglas D. Dunlop, E. Harcourt, N. Marriwala Ritu Khullar · 1997
An experimental set of tools that generate instruction set simulators,assemblers, and disassemblers from a single description wasdeveloped to test if retargetable development tools would work forcommercial DSP processors and microprocessors. The processorinstruction set was described using a language called nML. TheTMS320C50 DSP processor and the ARM7 microprocessor weremodeled in nML. The resulting instruction set models executeabout 25,000 instructions per second, and compiled instruction setsimulation models execute about 150,000 instructions per second.The viability of this approach and the deficiencies of nML are discussed.