Low complexity CMOS competitive array for approaching assignments
F. Gomez-Casraneda, Luis Martin Flores-Nava, Jose Antonio Moreno-Cadenas · 2002
This work presents a CMOS analog integrated circuit in which an array of 8/spl times/8 winner-take-all neural units or competitive units computes binary matrices as an approach to the solution of assignment problems. The small silicon area in this system results from using early low-complexity current-mode circuits. The dynamic performance for selecting winning units by this prototype analog integrated circuit that encodes permutation matrices is evaluated with PSpice simulations.