Exceeding test pattern limitation by multi-clock test methodology
Jang Jin Hwan, Kim Kyung Ho, Kye Bum Suk · AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360) · 2003
There are some limitations in the ASIC test. The maximum test pattern depth is one of them. A method to reduce the test pattern depth would be very useful. Hence the authors introduce a method to do this and the target ATE is ADVAN.