Formal verification of design correctness of sequential circuits based on theorem provers
Paolo Enrico Camurati, Tiziana Margaria, P. Prinetto · 2002
After a presentation of alternative time modeling techniques, the description techniques available in OTTER, a first-order logic proof environment at the different abstraction levels are presented. A discussion is presented of the methodology envisaged for the proof of correctness and its implementation in OTTER depending on the circuit characteristics and on the reasoning technique. Some experimental results are also reported.>