Dynamically reconfigurable VLD circuit
Kiyotaka Komoku, Takashi Miyake, Takayuki Morishita, Nobuo Sasaki · 2009
A dynamically reconfigurable VLD (variable length decode) circuit is proposed. In this circuit, several comparators decode at input bitstream in parallel. Furthermore it can also decode next code in same time, using some comparators. The rate of number of comparators used for parallel and next code decoding is variable and the reconfiguration can be executed dynamically.