A 65nm random and systematic yield ramp infrastructure utilizing a specialized addressable array with integrated analysis software
M. P. Karthikeyan, Stephen R. Fox, William Cote, Greg Yeric, M. Hall, Joaquín Ignacio Bogado García, B. Mitchell, E. Wolf, Samarth Agarwal · 2006
This paper describes a yield learning infrastructure that has been developed and deployed to help rapidly ramp 65nm random and systematic yield. This infrastructure consists of a 4Mb addressable-array test circuit with > 8000 unique test structures along with customized software and automated analysis routines to distill the large datasets generated. Examples of the successful application of this methodology are provided.