A digital neuro chip with adaptive segmentation quantizer neuron architecture (ASQA)
M. Fukuda, H. Nakahira, Shiro Sakiyama, Masakatsu Maruyama, T. Kouda, Taro Imagawa, S. Maruno · 2002
We discuss a chip which simulates a neural network and automatically generates optimum network structure according to input data. It handles 128 sub neural networks which compose a large scale neural network. By our original architecture, necessary memory size to get the same recognition performance as a conventional chip is reduced to 9%. It classifies up to 16.384 categories and solves large size problems such as Kanji recognition on a single chip. It consists of 250 K transistors on a 6.92 mm/spl times/7.08 mm chip by 0.5 /spl mu/m double metal CMOS technology.