Delay Test Techniques For Boundary Scan Based Archictures
Hoon Chang, Jacob A. Abraham · 1992
This paper proposes techniques for appl ing delay tests in a Boundary Scan environment. &e' limitation of current public instructions of IEEE 11 9.1 when used for delay test is described and an eicient delay test tech.nigue is presented. Delay tests for chips, their interconnection and the glue logic are proposed. An approach for a pi ang delay tests to Level Sensitive Scan Design basel clips with Boundary Scan is also presented.