Verification of FPGA internal resources
Alfredo Gardel, Ignácio Bravo, José Luis Lázaro Galilea, Beatriz Perez, Javier Baliñas, Álvaro Hernández · 2009
This paper presents the design of an evaluation system of an internal state of the FPGA (Field Programmable Gate Array). The system is divided in two parts, one part hardware and other software. The software part is based on the creation of various digital circuits to be implemented on a FUT (FPGA Under Test) and to be loaded on various test patterns to verify the operation of its various resources, and will be managed from a graphical interface created under CVI (C for Virtual Instrumentation). The hardware part consists of the creation of two boards that bear the resources to test and diagnosis. The first board contains an FPGA which will manage the test patterns and the results thereof, has been called Mother. The second board called FUT, will contain a FUT, and what will be on the test operation performed by the circuits previously created)