Distributed Loss Compensation for Low-latency On-chip Interconnects
Anup P. Jose, Ken L. Shepard · 2006
The use of distributed loss compensation for on-chip interconnects is discussed. Results are presented for a 14mm 3Gb/s on-chip link in 0.18μm CMOS with a measured latency of 12.1ps/mm and an energy dissipation of 2pJ/b with a BER-14. A 3times improvement in power consumption and a 1.5times improvement in latency over an optimally-repeated RC line is demonstrated