A VLSI architecture for real-time edge linking
A. Hajjar, T. Chen · IEEE Transactions on Pattern Analysis and Machine Intelligence · 1999
A real-time algorithm and its VLSI implementation for edge linking is presented. The linking process is based on the break points' directions and the weak level points. The proposed VLSI architecture is capable of outputting one pixel of the linked edge map per clock cycle with a latency of 11n+12 clock cycles, where n is the number of pixel columns in the image.