Co-simulation of SystemC TLM with RTL HDL for surveillance camera system verification
Jeongwoo Park, Bongchun Lee, Kyusam Lim, Jeong-Hun Kim, Suki Kim, Kwang‐Hyun Baek · 2008
Modern SoCs have the large scale and complexity. Modeling hardware architectures for SoCs usually requires pin-level and cycle-level descriptions by register transfer level(RTL). Hardware design at RTL takes too much effort to develop and simulate HDL code such as Verilog or VHDL. Therefore, a higher abstraction level is needed. Transaction level modeling (TLM) using SystemC addresses the limitations of pure RTL modeling methodologies. In this paper, we apply co-simulation of SystemC TLM with RTL HDL to a surveillance camera system using a one-bit motion detection algorithm for portable applications. The host controller interface (HCI) and the motion detection sensor (MDS) are implemented by SystemC TLM. API program is implemented by C++ program and the other blocks of this system are implemented by RTL HDL. To verify co-simulation, HCI, MDS, and API program are operated at PC and blocks implemented by RTL HDL are downloaded at FPGA board to support emulation.