Decimal Adders/Subtractors in FPGA: Efficient 6-input LUT Implementations
Martín Vázquez, Gustavo D. Sutter, Géry Jean Antoine Bioul, Jean‐Pierre Deschamps · 2009
This paper presents FPGA implementations of add/subtract algorithms for 10's complement BCD numbers. Carry-chain type circuits have been designed on 6-input LUT's Xilinx Virtex-5 FPGA technologies. Some new concepts are reviewed to compute the P and G functions for carry-chain optimization purposes. Designs are presented with the corresponding time performances and area consumption figures. Results have been compared with 2's complement binary implementations carried out on the same platform. Better time delays have been registered for decimal number within same range of operands.