Near optimal embedding of binary tree architecture in VLSI
Hee Yong Youn, A.D. Singh · 2003
An efficient scheme is presented for embedding a complete binary tree architecture in a two-dimensional array of processing elements. The scheme utilizes almost 100% of the processing elements in the array as actual computing elements, with small and asymptotically optimal propagation delay. The maximum edge length is optimal for trees with up to six levels. The scheme is compared with other designs proposed in the literature and shown to be significantly better.>