Hardware efficient base-4 systolic architecture for computing the discrete Fourier transform
J. Greg Nash · 2003
A systolic architecture is described for computing the 1-D discrete Fourier transform, which provides a significant reduction in array area by reducing the number of complex multipliers compared to previous systolic approaches. This design improvement is achieved by taking advantage of a more efficient computation scheme based on symmetries in the coefficient matrix and a radix-4 butterfly. Comparisons are provided with previous systolic architectures. Systolic architecture designs were created using a CAD tool able to find optimal non-uniform array designs starting from high-level coded descriptions of the algorithm.