A method of diagnosing single stuck‐at faults in combinational circuits
Teruhiko Yamada, Yoshiyuki Nakamura · Systems and Computers in Japan · 1992
Abstract A new method is proposed to diagnose single stuck‐at faults in combinational circuits. In this method, based on the operations of the nonfaulty circuit, first the possible faulty paths are examined from the primary outputs, at which errors have been observed, toward the primary inputs to narrow down the suspected faulty section. Then a fault simulation is conducted to deduce the fault location. According to the computational experiments it is expected that this method is faster than the conventional fault dictionary methods by about two orders of magnitude and the diagnosis time is almost proportional to the circuit size. Thus, this method is very effective for fault diagnosis of large‐scale circuits.