A layout driven test generation for CMOS combinational circuits
Utpal Kumar Bhattacharya, I. Sen Gupta · 2002
This paper presents a test generation scheme for CMOS combinational circuits. The fault model has been chosen from the layout description of the circuit as the set of faults that are more likely to occur. A divide-and-conquer strategy has been used for test generation, whereby explicit fault simulation is avoided over the entire circuit. The developed fault model and the test generation algorithms have been applied to some example circuits.>