A zero aliasing built-in self test technique for delay fault testing
Yiorgos E. Tsiatouhas, Themistoklis Haniotakis · 2003
A zero aliasing built-in self-test (BIST) approach to detect timing related failures in VLSI circuits is proposed. The BIST scheme is based on a transition detector and is able to detect timing related failures resulting in shorter than expected as well as larger than expected delay faults.