A 32-bit superscalar microprocessor with 64-bit processing and high bandwidth DRAM interface
M. Matsuo, Hiroyuki Kondo, Yukari Takata, S. Kobayashi, M. Satoh, T. Yoshida, Yuichi Saito, J. Hinata · 2002
This paper describes a 32-bit CISC superscalar microprocessor designed for high-end embedded applications, such as X-window terminals and printers. To realize high performance of processing a series of memory data such as a frame buffer and a character-string, we have used block-data-transfer and 64-bit processing to improve execution efficiency of multiple-operation instructions of the processor. 16-byte block read/write operations through a 32-bit external data bus have accomplished high bandwidth for DRAM access, even in the case of non-cacheable regions such as a frame buffer. In executing multiple-operation instructions, 64-bit processing has been realized by operating the dual execution circuits for superscalar executions and a 64-bit internal data bus under the control of a very long micro-instruction word. By using these techniques, we have enhanced the frame buffer manipulation performance of this processor 1.5 to 2 times.>