On-chip bus signaling using passive compensation
Yulei Zhang, Ling Zhang, Alina Deutsch, George A. Katopis, Daniel M. Dreps, James F. Buckwalter, E.S. Kuh, Chung‐Kuan Cheng · 2008
A new scheme for bus signaling using on-chip lossy transmission lines with passive compensation is introduced in this paper to address the performance limitation brought by the scaling issues of on-chip global wires. The new scheme is designed and optimized based on eye-diagram prediction algorithm and sequential quadratic programming (SQP) flow. We perform a case study to demonstrate feasibility of the proposed scheme. The results show that, at 45 nm technology node, the new scheme achieves 20.58 ps/mm transmission speed and has the power efficiency of 0.106 pJ/bit considering the crosstalk effects.