Methodology and reconfigurable architecture for effective placement of variable-size hardware tasks
Nicolas Marques, Hassan Rabah, Slaviša Jovanović, Eric Dabellani, Serge Weber · 2013
Dynamic partial reconfiguration (DPR) of FPGA-based architectures offers a high degree of flexibility and is often an appropriate solution for applications needing dynamically changing contexts. The standard design flow used for design of these architectures still suffer from a lack of adaptability when confronted with applications to implement consisting of variable-size hardware tasks or IP (Intellectual Property) cores. Thus induced heterogeneity may cause wrong placement of hardware tasks (IPs) on a chip leading to a sub-optimal use of available hardware resources and therefore a decrease in the system performances. This paper addresses the problems of effective design of reconfigurable regions on the FPGA device with regard to needed hardware resources for a given application. We propose a methodology allowing effective placement of variable-size IPs on reconfigurable regions which are sized to the smallest IP of a given application. Its validation and benefits are shown on the example of video transcoding from MPEG2 to H.264 video stream, especially in the case of reconfigurable region partitioning used to implement hardware tasks for the entropy encoding (CAVLC / VLC). The obtained results show a gain in hardware utilization resources up to 40% for given hardware tasks and the lesser context changing time (up to 2 times faster) which is driven by the size of the reconfigurable region used to task implementation.