Efficient systolic high speed architectures for delayed multipath two-dimensional FIR and IIR digital filtering
Hon Keung Kwan, M.T. Tsim · IEE Proceedings G Circuits Devices and Systems · 1990
In the paper, two novel efficient blocklevel systolic architectures for the high speed realisation of delayed multipath two-dimensional FIR and IIR digital filters are presented. In practice, difficulty arises in the implementation of an IIR digital filter because of the inherent timing constraint in its recursive loop. With the new transformation method presented in the paper, an extra loop delay is allowed in the recursive part of the multipath structure of an IIR digital filter. Consequently, the problem of the inherent timing constraint in the recursive loop is solved. Two methods for the stabilisation of the transformation method are also introduced. The resultant blocklevel systolic structures remove the global communication requirements, which further increases the efficiency of the final realisation.